(1) Field of the Invention
The present invention relates to a fabrication method used to create a stacked capacitor structure, for a DRAM device, in which the stacked capacitor structure is created after formation of DRAM interconnect metal structures.
(2) Description of the Prior Art
The objectives of the semiconductor industry are to continually improve device performance, while still attempting to decrease the manufacturing cost of specific semiconductor chips. These objectives have been in part realized by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, and thus limiting the amount of area the overlying STC structure can occupy, without interfering with neighboring cells.
Solutions to the shrinking design area, assigned to STC structures, have been addressed via novel semiconductor fabrication processes which result in an increase in surface area for only the lower, or storage electrode, of the STC structure, while maintaining the area original design area of the STC structure. One method for achieving this objective has been accomplished by creating lower electrodes with pillars, or protruding shapes of polysilicon, thus resulting in a greater electrode surface area then would have been achieved with conventional flat surfaces. Kim, in U.S. Pat. No. 5,447,882, describes such an STC structure, comprised of a lower electrode, formed by creating protruding polysilicon features, via patterning of a polysilicon layer, however the topography created with these novel STC configurations present difficulties for subsequent formation of overlying interconnect metal structures. For example thick insulator layers are needed for adequate coverage of the STC structure, which presents additional problems when opening vias in the thick insulator layer, and then attempting to fill the high aspect ratio via holes with metal. Thus the capacitor under bit line, (CUM), structure, can result in yield and reliability problems resulting from poor metal coverage, in high aspect ratio holes.
This invention will describe a process, and a structure, in which the capacitor structure is constructed after formation of the metal interconnect levels. After passivation of underlying metal interconnect structures with insulator layers, and planarization of the insulator layer, the stacked capacitor structure is formed over the passivated metal structures, (Capacitor Over Metalxe2x80x94COM), thus avoiding formation of metal interconnects over severe topologies created from an underlying STC structure.
It is an object of this invention to create a DRAM device, with an STC structure, in which the surface area of the lower electrode, of the STC structure is increased, without creating the high aspect ratios of metal via holes encountered using conventional capacitor under metal, (CUM), stacked capacitor structures.
It is another object of this invention to form the STC structure after the formation of metal interconnect structures, on a planarized, smooth top surface of an insulator layer, used on the underlying metal interconnect structures.
In accordance with the present invention a method for fabricating a DRAM device, with an STC structure that is formed after the formation of metal interconnect structures, has been developed. A transfer gate transistor comprised of: a thin gate insulator; a polysilicon gate structure; lightly doped source and drain regions; insulator spacers on the sidewalls of the polysilicon gate structure; and/or heavily doped source and drain regions; is formed on a semiconductor substrate. Polysilicon plugs are formed in a first insulator layer, contacting a source and drain region between polysilicon gate structures. A second insulator layer is deposited, followed by the formation of shallow, first level metal studs, located in shallow via holes that had been created in the second insulator layer, with the shallow, first level metal studs contacting the polysilicon plugs. A deep via hole, however shallower than via holes used in conventional CUM DRAM structures, is also formed in the second, and in the first insulator layers, allowing a deep, first level metal stud to be created, with the deep, first level metal stud contacting a region of the semiconductor substrate, exposed in the deep via hole. Metal structures are next formed, and used for: a bit line structure contacting a first, shallow, first level metal stud; a first level metal interconnect structure, contacting the deep, first level metal stud; and for a metal plug, contacting a second, shallow, first metal stud. A third insulator layer is deposited, and planarized, followed by the opening of a via hole, exposing the top surface of the first level metal interconnect structure. A second level metal stud is next formed in the via hole in the third insulator layer. A second level interconnect structure is next formed, contacting a second level metal stud, which in turn overlays and contacts a first level metal interconnect structure. A fourth insulator layer is deposited followed by creation of a third level metal stud. A stacked capacitor structure is finally formed on the fourth insulator layer, contacting the third level metal stud, in a region in which the third level metal stud overlays the metal plug, allowing contact between the STC structure and a source and drain region, of the transfer gate transistor. The capacitor structure, and process used for formation, described in this invention is shown overlaying only two levels of metal interconnect structures, however this invention can be applied to overlay as many metal interconnect levels as desired.